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K4R571669D/K4R881869D
Direct RDRAMTM
256/288Mbit RDRAM(D-die)
512K x 16/18bit x 32s banks Direct RDRAMTM
Version 1.4 July 2002
Page -1
Version 1.4 July 2002
K4R571669D/K4R881869D
Change History
Direct RDRAMTM
Version 1.4( July 2002)
- First Copy ( Version 1.4 is named to unify the version of component and device operation datasheets) - Based on the 256/288Mb A-die RDRAM Version 1.4
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Version 1.4 July 2002
K4R571669D/K4R881869D
Overview
The RDRAM device is a general purpose high-performance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. The 256/288-Mbit RDRAM devices are extremely highspeed CMOS DRAMs organized as 16M words by 16 or 18 bits. The use of Rambus Signaling Level (RSL) technology permits up to 1066 MHz transfer rates while using conventional system and board design technologies. RDRAM devices are capable of sustained data transfers up to 0.938ns per two bytes (7.5ns per sixteen bytes). The architecture of RDRAM devices allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The RDRAM device's 32 banks support up to four simultaneous transactions. System oriented features for mobile, graphics and large memory systems include power management, byte masking, and x18 organization. The two data bits in the x18 organization are general and can be used for additional storage and bandwidth or for error correction.
Direct RDRAMTM
SAMSUNG 230 K4RXXXX69D-Fxxx
Figure 1: Direct RDRAM CSP Package The 256/288-Mbit RDRAM devices are offered in a CSP horizontal package suitable for desktop as well as lowprofile add-in card and mobile applications.
Key Timing Parameters/Part Numbers
Speed Organization
Bin I/O Freq. MHz 1066 1066 1066 800 800 1066 1066 1066 800 800 tRAC (Row Access Time) ns 32P 32 35 40 45 32P 32 35 40 45
Features
Highest sustained bandwidth per DRAM device
Part Number
- 2.1GB/s sustained data transfer rate - Separate control and data buses for maximized efficiency - Separate row and column control buses for easy scheduling and highest performance - 32 banks: four transactions can take place simultaneously at full bandwidth data rates
Low latency features
-CT9 -CN9 512Kx16x32sa -CM9 -CM8 -CK8 -CT9 -CN9 512Kx18x32s -CM9 -CM8 -CK8
K4R571669D-FbCcT9 K4R571669D-FCN9 K4R571669D-FCM9 K4R571669D-FCM8 K4R571669D-FCK8 K4R881869D-FCT9 K4R881869D-FCN9 K4R881869D-FCM9 K4R881869D-FCM8 K4R881869D-FCK8
- Write buffer to reduce read latency - 3 precharge mechanisms for controller flexibility - Interleaved transactions
Advanced power management:
- Multiple low power states allows flexibility in power consumption versus time to transition to active state - Power-down self-refresh
Organization: 2kbyte pages and 32 banks, x 16/18
a."32s" - 32 banks which use a "split" bank architecture. b."F" - WBGA package. c."C" - RDRAM core uses normal power self refresh.
- x18 organization allows ECC configurations or increased storage/bandwidth - x16 organization for low cost applications
Uses Rambus Signaling Level (RSL) for up to 1066MHz
operation
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Version 1.4 July 2002
K4R571669D/K4R881869D
Pinouts and Definitions
Center-Bonded Devices
These tables shows the pin assignments of the center-bonded RDRAM package. The mechanical dimensions of this
Direct RDRAMTM
package are shown in a later section. Refer to Section "Center-Bonded WBGA Package" on page 18. Note - pin #1 is at the A1 position.
Table 1: Center-Bonded Device (top view)
10 9 8 7 6 5 4 3 2 1 A
ROW COL
VDD GND GND VDD GND GND GND GND GND VDD GND GND DQA6 DQA4 DQA2 DQA0 CFM CFMN RQ6 RQ4 RQ2 RQ0 DQB0 DQB2 DQB4 DQB6 GND GND GND VDD DQA8 CMD VDD DQA5 GND GNDa GNDa VDD CTM VDD RQ7 GND GND VDD RQ1 VDD DQB1 GND GND VCMOS DQB7 VDD DQB8 GND VDD GND VDD GND VDD VDD VDD VDD GND VDD
VDD
DQA7
DQA3
DQA1
CTMN
RQ5
RQ3
DQB3
DQB5
VDD
VDD
GND
SCK
VCMOS
GND
VDD
GND
VDDa
VREF
GND
VDD
GND
GND
VDD
SIO0
SIO1
GND
VDD
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
T
U
SAMSUNG 230 K4RXXXX69D-Fxxx
Top View
Chip
The pin #1(ROW 1, COL A) is located at the A1 position on the top side and the A1 position is marked by the marker " ".
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Version 1.4 July 2002
K4R571669D/K4R881869D
Direct RDRAMTM
Table 2: Pin Description
Signal SIO1,SIO0 CMD I/O I/O I Type CMOSa CMOSa # Pins center 2 1 Description Serial input/output. Pins for reading from and writing to the control registers using a serial access protocol. Also used for power management. Command input. Pins used in conjunction with SIO0 and SIO1 for reading from and writing to the control registers. Also used for power management. Serial clock input. Clock source used for reading from and writing to the control registers Supply voltage for the RDRAM core and interface logic. Supply voltage for the RDRAM analog circuitry. Supply voltage for CMOS input/output pins. Ground reference for RDRAM core and interface. Ground reference for RDRAM analog circuitry. Data byte A. Nine pins which carry a byte of read or write data between the Channel and the RDRAM device. DQA8 is not used (no connection) by RDRAM device with a x16 organization. Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity Logic threshold reference voltage for RSL signals Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. Row access control. Three pins containing control and address information for row accesses. Column access control. Five pins containing control and address information for column accesses. Data byte B. Nine pins which carry a byte of read or write data between the Channel and the RDRAM device. DQB8 is not used (no connection) by RDRAM device with a x16 organization.
SCK VDD VDDa VCMOS GND GNDa DQA8..DQA0
I
CMOSa
1 24 1 2 28 2
I/O
RSLb
9
CFM CFMN VREF CTMN CTM RQ7..RQ5 or ROW2..ROW0 RQ4..RQ0 or COL4..COL0 DQB8.. DQB0
I I
RSLb RSLb
1 1 1
I I I I I/O
RSLb RSLb RSLb RSLb RSLb
1 1 3 5 9
Total pin count per package
92
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero. b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
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Version 1.4 July 2002
K4R571669D/K4R881869D
Direct RDRAMTM
DQB8..DQB0 9
RQ7..RQ5 or ROW2..ROW0 3
CTM CTMN SCK,CMD SIO0,SIO1 CFM CFMN 2 2 RCLK
RQ4..RQ0 or COL4..COL0 5
DQA8..DQA0 9 RCLK
1:8 Demux TCLK Packet Decode ROWR ROWA 11 5 5 9 ROP DR BR AV
Match
1:8 Demux RCLK Control Registers 6 REFR
Power Modes
COLX 5 5
Packet Decode COLC 5 5 5 7 C
8
COLM 8
R
DEVID
XOP DX BX COP DC BC M S
Match XOP Decode Match
MB MA
Mux Row Decode
DM
Write Buffer Mux Mux
PRER ACT Sense Amp 64x72 Internal DQB Data Path
SAmp SAmp SAmp 1/2 0/1 0
PREX
Column Decode & Mask
DRAM Core 64x72 512x128x144 Bank 0 Bank 1 Bank 2 *** 64x72 72
SAmp SAmp SAmp 0 0/1 1/2
PREC
RD, WR
72
Internal DQA Data Path
72
72
RCLK
9
9
***
9
***
9
RCLK
SAmp SAmp SAmp 15 14/15 13/14
Bank 13 Bank 14 Bank 15
SAmp SAmp SAmp 13/14 14/15 15
Write Buffer
Write Buffer
1:8 Demux
9
1:8 Demux
9
SAmp SAmp SAmp 16 16/17 17/18
SAmp SAmp SAmp 17/18 16/17 16
Bank 16 Bank 17 Bank 18 ***
TCLK
9
9
TCLK
***
8:1 Mux
***
8:1 Mux
9
9
SAmp SAmp SAmp 31 30/31 29/30
Bank 29 Bank 30 Bank 31
Figure 2: 256/288-Mbit (512Kx16/18x32s) RDRAM Device Block Diagram
SAmp SAmp SAmp 29/30 30/31 31
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Version 1.4 July 2002
K4R571669D/K4R881869D
General Description
Figure 2 is a block diagram of the 256/288-Mbit RDRAM device. It consists of two major blocks: a "core" block built from banks and sense amps similar to those found in other types of DRAM, and a Direct RambusTM interface block which permits an external controller to access this core at up to 2.1GB/s.
Direct RDRAMTM
amps of the RDRAM device. These pins are de-multiplexed into a 24-bit ROWA (row-activate) or ROWR (row-operation) packet.
COL Pins: The principle use of these five pins is to
manage the transfer of data between the DQA/DQB pins and the sense amps of the RDRAM device. These pins are demultiplexed into a 23-bit COLC (column-operation) packet and either a 17-bit COLM (mask) packet or a 17-bit COLX (extended-operation) packet.
Control Registers: The CMD, SCK, SIO0, and SIO1 pins appear in the upper center of Figure 2. They are used to write and read a block of control registers. These registers supply the RDRAM configuration information to a controller and they select the operating modes of the device. The REFR value is used for tracking the last refreshed row. Most importantly, the five bit DEVID specifies the device address of the RDRAM device on the Channel. Clocking: The CTM and CTMN pins (Clock-To-Master)
generate TCLK (Transmit Clock), the internal clock used to transmit read data. The CFM and CFMN pins (Clock-FromMaster) generate RCLK (Receive Clock), the internal clock signal used to receive write data and to receive the ROW and COL pins.
ACT Command: An ACT (activate) command from an ROWA packet causes one of the 512 rows of the selected bank to be loaded to its associated sense amps (two 512 bytes sense amps for DQA and two for DQB). PRER Command: A PRER (precharge) command from
an ROWR packet causes the selected bank to release its two associated sense amps, permitting a different row in that bank to be activated, or permitting adjacent banks to be activated.
RD Command: The RD (read) command causes one of the 128 dualocts of one of the sense amps to be transmitted on the DQA/DQB pins of the Channel. WR Command: The WR (write) command causes a
dualoct received from the DQA/DQB data pins of the Channel to be loaded into the write buffer. There is also space in the write buffer for the BC bank address and C column address information. The data in the write buffer is automatically retired (written with optional bytemask) to one of the 128 dualocts of one of the sense amps during a subsequent COP command. A retire can take place during a RD, WR, or NOCOP to another device, or during a WR or NOCOP to the same device. The write buffer will not retire during a RD to the same device. The write buffer reduces the delay needed for the internal DQA/DQB data path turnaround.
DQA,DQB Pins: These 16/18 pins carry read (Q) and write (D) data across the Channel. They are multiplexed/demultiplexed from/to two 64/72-bit data paths (running at one-eighth the data frequency) inside the RDRAM. Banks: The 32Mbyte core of the RDRAM device is
divided into thirty two 1Mbyte banks, each organized as 512 rows, with each row containing 128 dualocts, and each dualoct containing 16/18 bytes. A dualoct is the smallest unit of data that can be addressed.
Sense Amps: The RDRAM device contains 34 sense
amps. Each sense amp consists of 1kbyte of fast storage (512 bytes for DQA and 512 bytes for DQB) and can hold onehalf of one row of one bank of the RDRAM device. The sense amp may hold any of the 1024 half-rows of an associated bank. However, each sense amp is shared between two adjacent banks of the RDRAM device (except for sense amps 0, 15, 16, and 31). This introduces the restriction that adjacent banks may not be simultaneously accessed.
PREC Precharge: The PREC, RDA and WRA commands are similar to NOCOP, RD and WR, except that a precharge operation is performed at the end of the column operation. These commands provide a second mechanism for performing precharge. PREX Precharge: After a RD command, or after a WR command with no byte masking (M=0), a COLX packet may be used to specify an extended operation (XOP). The most important XOP command is PREX. This command provides a third mechanism for performing precharge.
RQ Pins: These pins carry control and address information. They are broken into two groups. RQ7..RQ5 are also called ROW2..ROW0, and are used primarily for controlling row accesses. RQ4..RQ0 are also called COL4..COL0, and are used primarily for controlling column accesses.
ROW Pins: The principle use of these three pins is to
manage the transfer of data between the banks and the sense
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Version 1.4 July 2002
K4R571669D/K4R881869D
Packet Format
Figure 3 shows the formats of the ROWA and ROWR packets on the ROW pins. Table 3 describes the fields which comprise these packets. DR4T and DR4F bits are encoded to contain both the DR4 device address bit and a framing bit which allows the ROWA or ROWR packet to be recognized by the RDRAM device.
Direct RDRAMTM
The AV (ROWA/ROWR packet selection) bit distinguishes between the two packet types. Both the ROWA and ROWR packet provide a five bit device address and a five bit bank address. An ROWA packet uses the remaining bits to specify a nine bit row address, and the ROWR packet uses the remaining bits for an eleven bit opcode field. Note the use of the "RsvX" notation to reserve bits for future address field extension.
Table 3: Field Description for ROWA Packet and ROWR Packet
Field DR4T,DR4F DR3..DR0 BR4..BR0 AV R8..R0 ROP10..ROP0 Description Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit. Device address for ROWA or ROWR packet. Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the RDRAM device. Selects between ROWA packet (AV=1) and ROWR packet (AV=0). Row address for ROWA packet. RsvR denotes bits ignored by the RDRAM device. Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions.
Figure 3 also shows the formats of the COLC, COLM, and COLX packets on the COL pins. Table 4 describes the fields which comprise these packets. The COLC packet uses the S (Start) bit for framing. A COLM or COLX packet is aligned with this COLC packet, and is also framed by the S bit. The 23 bit COLC packet has a five bit device address, a five bit bank address, a seven bit column address, and a four bit opcode. The COLC packet specifies a read or write command, as well as some power management commands.
The remaining 17 bits are interpreted as a COLM (M=1) or COLX (M=0) packet. A COLM packet is used for a COLC write command which needs bytemask control. The COLM packet is associated with the COLC packet from at least tRTR earlier. A COLX packet may be used to specify an independent precharge command. It contains a five bit device address, a five bit bank address, and a five bit opcode. The COLX packet may also be used to specify some housekeeping and power management commands. The COLX packet is framed within a COLC packet but is not otherwise associated with any other packet.
Table 4: Field Description for COLC Packet, COLM Packet, and COLX Packet
Field S DC4..DC0 BC4..BC0 C6..C0 COP3..COP0 M MA7..MA0 MB7..MB0 DX4..DX0 BX4..BX0 XOP4..XOP0 Description Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets. Device address for COLC packet. Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drives 0 ' s). Column address for COLC packet. RsvC denotes bits ignored by the RDRAM device. Opcode field for COLC packet. Specifies read, write, precharge, and power management functions. Selects between COLM packet (M=1) and COLX packet (M=0). Bytemask write control bits. 1=write, 0=no-write. MA0 controls the earliest byte on DQA8..0. Bytemask write control bits. 1=write, 0=no-write. MB0 controls the earliest byte on DQB8..0. Device address for COLX packet. Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drives 0' s). Opcode field for COLX packet. Specifies precharge, IOL control, and power management functions.
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K4R571669D/K4R881869D
Direct RDRAMTM
T0
T1
T2
T3
T8
T9
T10
T11
CTM/CFM
CTM/CFM
ROW2 DR4T DR2 BR0 BR3 RsvR R8 ROW1 ROW0
DR4F DR1 BR1 BR4 RsvR DR3 DR0 BR2 RsvB AV=1 R7 R6
R5
R2
ROW2 DR4T DR2 BR0 BR3 ROW1 ROW0
ROP10 ROP8 ROP5 ROP2
R4 R3
R1 R0
DR4F DR1 BR1 BR4 ROP9 ROP7 ROP4 ROP1 DR3 DR0 BR2 RsvB AV=0 ROP6 ROP3 ROP0
ROWA Packet
T0 T1 T2 T3
ROWR Packet
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
CTM/CFM
DC4 DC3 DC2 COP1 DC1 COP0 DC0 COP2 S=1 C6 C5 RsvB BC2 BC4 BC1 COP3 BC3 BC0 C4 C3 C2 C1 C0
CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA8..0 DQB8..0
ACT a0 PRER c0
COL4 COL3 COL2 COL1 COL0
tPACKET
WR b1 MSK (b1) PREX d0
COLC Packet
T8 T9 T10 T11 T12 T13 T14 T15
CTM/CFM
CTM/CFM
COL4 COL3 COL2 COL1 COL0
a
S=1a MA7 MA5 MA3 MA1 M=1 MA6 MA4 MA2 MA0 MB7 MB4 MB1 MB6 MB3 MB0 MB5 MB2
COL4 COL3 COL2 COL1 COL0
S=1b DX4 XOP4 RsvB BX1 M=0 DX3 XOP3 BX4 BX0 DX2 XOP2 BX3 DX1 XOP1 BX2 DX0 XOP0
b The
The COLM is associated with a previous COLC, and is aligned with the present COLC, indicated by the Start bit (S=1) position.
COLM Packet Figure 3: Packet Formats
COLX Packet
COLX is aligned with the present COLC, indicated by the Start bit (S=1) position.
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K4R571669D/K4R881869D
Field Encoding Summary
Table 5 shows how the six device address bits are decoded for the ROWA and ROWR packets. The DR4T and DR4F encoding merges a fifth device bit with a framing bit. When neither bit is asserted, the device is not selected. Note that a
Direct RDRAMTM
broadcast operation is indicated when both bits are set. Broadcast operation would typically be used for refresh and power management commands. If the device is selected, the DM (DeviceMatch) signal is asserted and an ACT or ROP command is performed.
Table 5: Device Field Encodings for ROWA Packet and ROWR Packet
DR4T 1 0 1 0 DR4F 1 1 0 0 Device Selection All devices (broadcast) One device selected One device selected No packet present Device Match signal (DM) DM is set to 1 DM is set to 1 if {DEVID4..DEVID0} == {0,DR3..DR0} else DM is set to 0 DM is set to 1 if {DEVID4..DEVID0} == {1,DR3..DR0} else DM is set to 0 DM is set to 0
Table 6 shows the encodings of the remaining fields of the ROWA and ROWR packets. An ROWA packet is specified by asserting the AV bit. This causes the specified row of the specified bank of this device to be loaded into the associated sense amps. An ROWR packet is specified when AV is not asserted. An 11 bit opcode field encodes a command for one of the banks of this device. The PRER command causes a bank and its two associated sense amps to precharge, so another row or an adjacent bank may be activated. The REFA (refresh-activate) command is similar to the ACT command, except the
row address comes from an internal register REFR, and REFR is incremented at the largest bank address. The REFP (refresh-precharge) command is identical to a PRER command. The NAPR, NAPRC, PDNR, ATTN, and RLXR commands are used for managing the power dissipation of the RDRAM device and are described in more detail in "Power State Management" on page 50. The TCEN and TCAL commands are used to adjust the output driver slew rate and they are described in more detail in "Current and Temperature Control" on page 56.
Table 6: ROWA Packet and ROWR Packet Field Encodings
ROP10..ROP0 Field DMa 0 1 1 1 1 1 1 1 1 1 1 1 1 AV 10 1 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2:0 --ACT 0 1 0 0 0 0 x x 0 0 0 0 1 1 0 0 0 x x 0 0 0 xc 0 0 0 1 1 x x 0 0 0 x 0 0 1 0 1 x x 0 0 0 x x x x x x 0 1 x x 0 000 000 000 000 000 000 000 000 001 010 000 PRER REFA REFP PDNR NAPR NAPRC ATTNb RLXR TCAL TCEN NOROP No operation. Activate row R8..R0 of bank BR4..BR0 of device and move device to ATTNb. Precharge bank BR4..BR0 of this device. Refresh (activate) row REFR8..REFR0 of bank BR4..BR0 of device. Increment REFR if BR4..BR0 = 11111 (see Figure 52). Precharge bank BR4..BR0 of this device after REFA (see Figure 52). Move this device into the powerdown (PDN) power state (see Figure 49). Move this device into the nap (NAP) power state (see Figure 49). Move this device into the nap (NAP) power state conditionally Move this device into the attention (ATTN) power state (see Figure 47). Move this device into the standby (STBY) power state (see Figure 48). Temperature calibrate this device (see Figure 55). Temperature calibrate/enable this device (see Figure 55). No operation. Name Command Description
Row address 1 0 1 x x x x x 0 0 0 1 0 0 x x x x x 0 0 0 0 0 1 0 0 0 x x 0 0 0
a. The DM (Device Match signal) value is determined by the DR4T,DR4F, DR3..DR0 field of the ROWA and ROWR packets. See Table 5. b. The ATTN command does not cause a RLX-to-ATTN transition for a broadcast operation (DR4T/DR4F=1/1). c. An "x" entry indicates which commands may be combined. For instance, the three commands PRER/NAPRC/RLXR may be specified in one ROP value (011000111000).
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K4R571669D/K4R881869D
Table 7 shows the COP field encoding. The device must be in the ATTN power state in order to receive COLC packets. The COLC packet is used primarily to specify RD (read) and WR (write) commands. Retire operations (moving data from the write buffer to a sense amp) happen automatically. See Figure 18 for a more detailed description.
Direct RDRAMTM
The COLC packet can also specify a PREC command, which precharges a bank and its associated sense amps. The RDA/WRA commands are equivalent to combining RD/WR with a PREC. RLXC (relax) performs a power mode transition. See "Power State Management" on page 50.
Table 7: COLC Packet Field Encodings
S 0 1 1 1 1 1 1 1 1 1 1 DC4.. DC0 (select device)a ---/= (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) COP3..0 --------x000b x001 x010 x011 x100 x101 x110 x111 1xxx NOCOP WR RSRV RD PREC WRA RSRV RDA RLXC Name No operation. Retire write buffer of this device. Retire write buffer of this device. Retire write buffer of this device, then write column C6..C0 of bank BC4..BC0 to write buffer. Reserved, no operation. Read column C6..C0 of bank BC4..BC0 of this device. Retire write buffer of this device, then precharge bank BC4..BC0 (see Figure 15). Same as WR, but precharge bank BC4..BC0 after write buffer (with new data) is retired. Reserved, no operation. Same as RD, but precharge bank BC4..BC0 afterward. Move this device into the standby (STBY) power state (see Figure 48). Command Description
a. "/=" means not equal, "==" means equal. b. An "x" entry indicates which commands may be combined. For instance, the two commands WR/RLXC may be specified in one COP value (1001).
Table 8 shows the COLM and COLX field encodings. The M bit is asserted to specify a COLM packet with two 8 bit bytemask fields MA and MB. If the M bit is not asserted, an COLX is specified. It has device and bank address fields, and an opcode field. The primary use of the COLX packet is to permit an independent PREX (precharge) command to be
specified without consuming control bandwidth on the ROW pins. It is also used for the CAL(calibrate) and SAM (sample) current control commands (see "Current and Temperature Control" on page 56), and for the RLXX power mode command (see "Power State Management" on page 50).
Table 8: COLM Packet and COLX Packet Field Encodings
M 1 0 0 0 0 0 0 0 DX4 .. DX0 (selects device) ---/= (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) 00000 1xxx0a x10x0 x11x0 xxx10 xxxx1 XOP4..0 Name MSK NOXOP PREX CAL CAL/SAM RLXX RSRV Command Description MB/MA bytemasks used by WR/WRA. No operation. No operation. Precharge bank BX3..BX0 of this device (see Figure 15). Calibrate (drive) IOL current for this device (see Figure 54). Calibrate (drive) and Sample ( update) IOL current for this device (see Figure 54). Move this device into the standby (STBY) power state (see Figure 48). Reserved, no operation.
a. An "x" entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (10010).
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K4R571669D/K4R881869D
Electrical Conditions
Table 9: Electrical Conditions
Symbol
TJ VDD, VDDA VDD,N, VDDA,N vDD,N, vDDA,N VCMOSa VREF VDIL
Direct RDRAMTM
Parameter and Conditions
Junction temperature under bias Supply voltage Supply voltage droop (DC) during NAP interval (tNLIMIT) Supply voltage ripple (AC) during NAP interval (tNLIMIT) Supply voltage for CMOS pins (2.5V controllers) Supply voltage for CMOS pins (1.8V controllers) Reference voltage RSL data input - low voltage @ tCYCLE=1.875ns RSL data input - low voltage @ tCYCLE=2.50ns
Min
2.50 - 0.13 -2.0 VDD 1.80 - 0.1 1.40 - 0.2 VREF - 0.5 VREF - 0.5 VREF + 0.15 VREF + 0.2 0.67 1.3 0.35 0.225 0.3c
Max
100 2.50 + 0.13 2.0 2.0 VDD 1.80 + 0.2 1.40 + 0.2 VREF - 0.15
Unit
C V % % V V V V
VREF - 0.2 VREF + 0.5 V VREF + 0.5 1.00 1.8 1.00 1.00 VCMOS/2 - 0.25 VCMOS+0.3
d
VDIH
RSL data input - high voltageb @ tCYCLE=1.875ns RSL data input - high voltageb @ tCYCLE=2.50ns
RDA VCM VCIS,CTM VCIS,CFM VIL,CMOS VIH,CMOS
RSL data asymmetry : RDA = (VDIH - VREF) / (VREF - VDIL) RSL clock input - common mode VCM = (VCIH+VCIL)/2 RSL clock input swing: VCIS = VCIH - VCIL (CTM,CTMN pins). RSL clock input swing: VCIS = VCIH - VCIL (CFM,CFMN pins). CMOS input low voltage CMOS input high voltage
V V V V V
VCMOS/2 + 0.25
a. VCMOS must remain on as long as VDD is applied and cannot be turned off. b. VDIH is typically equal to VTERM (1.8V0.1V) under DC conditions in a system. c. Voltage undershoot is limited to -0.7V for a duration of less than 5ns. d. Voltage overshoot is limited toVCMOS +0.7V for a duration of less than 5ns
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Version 1.4 July 2002
K4R571669D/K4R881869D
Electrical Characteristics
Table 10: Electrical Characteristics
Symbol JC IREF IOH IALL RSL IOL current @ tCYCLE= 2.50ns VOL = 0.9V, VDD,MIN , TJ,MAX IOL rOUT IOL,NOM RSL IOL current resolution step Dynamic output impedance @ VOL= 0.9V RSL IOL current @ VOL = 1.0V RSL IOL current @ VOL = II,CMOS VOL,CMOS VOH,CMOS
b,c@
Direct RDRAMTM
Parameter and Conditions Junction-to-Case thermal resistance VREF current @ VREF,MAX RSL output high current @ (0VOUTVDD) RSL IOL current @ tCYCLE= 1.875ns VOL = 0.9V, VDD,MIN , TJ,MAX
a a
Min -10 -10 32.0 30.0 150 27.1 26.6 -10.0 VCMOS-0.3
Max 0.5 10 10 90.0
Unit C/Watt A A mA
90.0 1.5 30.1 mA 30.6 10.0 0.3 A V V mA
tCYCLE=1.875ns
1.0Vb,c
@ tCYCLE=2.50ns
CMOS input leakage current @ (0VI,CMOSVCMOS) CMOS output voltage @ IOL,CMOS= 1.0mA CMOS output high voltage @ IOH,CMOS= -0.25mA
a. This measurement is made in manual current control mode; i.e. with all output device legs sinking current. b. This measurement is made in automatic current control mode after at least 64 current control calibration operations to a device and after CCA and CCB are initialized to a value of 64. This value applies to all DQA and DQB pins. c. This measurement is made in automatic current control mode in a 25 test system with VTERM= 1.714V and VREF= 1.357V and with the ASYMA and ASYMB register fields set to 0.
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Version 1.4 July 2002
K4R571669D/K4R881869D
Timing Conditions
Table 11: Timing Conditions
Symbol
tCYCLE CTM and CFM cycle times (-800) tCR, tCF tCH, tCL CTM and CFM input rise and fall times. Use the minimum value of these parameters during testing. CTM and CFM high and low times CTM-CFM differential (MSE/MS=0/0) CTM-CFM differential (MSE/MS=1/1)a CTM-CFM differential only for 1.875ns (MSE/MS=1/0) tDCW tDR, tDF Domain crossing window DQA/DQB/ROW/COL input rise/fall times (20% to 80%). Use the minimum value of these parameters during testing. DQA/DQB/ROW/COL-to-CFM set/hold @ t CYCLE=1.875ns tS, tH DQA/DQB/ROW/COL-to-CFM set/hold @ t CYCLE=2.50ns tDR1, tDF1 tDR2, tDF2 SIO0, SIO1 input rise and fall times CMD, SCK input rise and fall times SCK cycle time - Serial control register transactions tCYCLE1 SCK cycle time - Power transitions @ t CYCLE=1.875ns SCK cycle time - Power transitions @ t CYCLE=2.50ns SCK high and low times @ t CYCLE=1.875ns tCH1, tCL1 SCK high and low times @ t CYCLE=2.50ns CMD setup time to SCK rising or falling edged @ t CYCLE=1.875ns tS1 CMD setup time to SCK rising or falling tH1 tS2 tH2 tS3 tH3 tS4 tH4 tNPQ tREADTOCC tCCSAMTOREAD tCE edged @ t CYCLE=2.50ns 4.25 1.0 1.25 1 40 40 0 5.5 -1 5 4 12 8 2 2.50 0.2 40% 0.0 0.9 -0.1 -0.1 0.2 0.160b 0.200b.c 1000 7.5 10 3.5 3.33 0.5 60% 1.0 1.0 0.1 0.1 0.45 -
Direct RDRAMTM
Parameter
CTM and CFM cycle times (-1066)
Min
1.875
Max
2.5
Unit
ns
Figure(s)
Figure 56
ns tCYCLE tCYCLE
Figure 56 Figure 56
tTR
Figure 43 Figure 56
tCYCLE ns
Figure 62 Figure 57
ns 5.0 2.0 ns ns ns ns
Figure 57 Figure 59 Figure 59
Figure 59
Figure 59
ns ns ns ns ns ns tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE
Figure 59 Figure 59 Figure 59 Figure 59 Figure 50 Figure 60 Figure 50 Figure 50 Figure 49 Figure 54 Figure 54 Figure 50
CMD hold time to SCK rising or falling edged SIO0 setup time to SCK falling edge SIO0 hold time to SCK falling edge PDEV setup time on DQA5..0 to SCK rising edge. PDEV hold time on DQA5..0 to SCK rising edge. ROW2..0, COL4..0 setup time for quiet window ROW2..0, COL4..0 hold time for quiet windowe Quiet on ROW/COL bits during NAP/PDN entry Offset between read data and CC packets (same device) Offset between CC packet and read data (same device) CTM/CFM stable before NAP/PDN exit
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Version 1.4 July 2002
K4R571669D/K4R881869D
Table 11: Timing Conditions
Symbol
tCD tFRM tNLIMIT tREF tBURST tCCTRL tTEMP tTCEN tTCAL tTCQUIET tPAUSE
Direct RDRAMTM
Parameter
CTM/CFM stable after NAP/PDN entry ROW packet to COL packet ATTN framing delay Maximum time in NAP mode Refresh interval Interval after PDN or NAP (with self-refresh) exit in which all banks of the RDRAM device must be refreshed at least once. Current control interval Temperature control interval TCE command to TCAL command TCAL command to quiet window Quiet window (no read data) RDRAM device delay (no RSL operations allowed)
Min
100 7
Max
10.0 32 200
Unit
tCYCLE tCYCLE s ms s ms/tCYCLE ms tCYCLE tCYCLE tCYCLE s
Figure(s)
Figure 49 Figure 48 Figure 47 Figure 52 Figure 53 Figure 54 Figure 55 Figure 55 Figure 55 Figure 55
34 tCYCLE
100ms 100
150 2 140
2 200.0
page 38
a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0. b. tS,MIN and tH,MIN for other tCYCLE values can be interpolated between or extrapolated from the timings at the 2 specified t CYCLE values. c. This parameter also applies to a-1066 part when operated with tCYCLE = 2.50ns d. With VIL,CMOS=0.5VCMOS-0.4V and VIH,CMOS=0.5VCMOS+0.4V e. Effective hold becomes tH4'=tH4+[PDNXA*64*tSCYCLE+tPDNXB,MAX]-[PDNX*256*tSCYCLE] if [PDNX*256*tSCYCLE] < [PDNXA*64*tSCYCLE+tPDNXB,MAX]. See Figure 50.
Page 13
Version 1.4 July 2002
K4R571669D/K4R881869D
Timing Characteristics
Table 12: Timing Characteristics
Symbol Parameter CTM-to-DQA/DQB output time @ tCYCLE=1.875ns tQ CTM-to-DQA/DQB output time @ tCYCLE=2.5ns DQA/DQB output rise and fall times @ tCYCLE=1.875ns tQR, tQF DQA/DQB output rise and fall times @ tCYCLE=2.5ns tQ1 tHR tQR1, tQF1 tPROP1 tNAPXA tNAPXB tPDNXA tPDNXB tAS tSA tASN tASP SCK(neg)-to-SIO0 delay @ CLOAD,MAX = 20pF (SD read data valid). SCK(pos)-to-SIO0 delay @ CLOAD,MAX = 20pF (SD read data hold). SIOOUT rise/fall @ CLOAD,MAX = 20pF SIO0-to-SIO1 or SIO1-to-SIO0 delay @ CLOAD,MAX = 20pF NAP exit delay - phase A NAP exit delay - phase B PDN exit delay - phase A PDN exit delay - phase B ATTN-to-STBY power state delay STBY-to-ATTN power state delay ATTN/STBY-to-NAP power state delay ATTN/STBY-to-PDN power state delay 0.2 2 Min -0.195a -0.260a,b 0.2
Direct RDRAMTM
Max +0.195a +0.260a,b 0.32
Unit
Figure(s)
ns
Figure 58
ns 0.45 10 12 20 50 40 4 9000 1 0 8 8 ns ns ns ns ns ns s tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE
Figure 58 Figure 61 Figure 61 Figure 61 Figure 61 Figure 50 Figure 50 Figure 50 Figure 50 Figure 48 Figure 48 Figure 49 Figure 49
a. tQ,MIN and tQ,MAX for other tCYCLE values can be interpolated between or extrapolated from the timings at the 3 specified tCYCLE values. b.This parameter also applies to a-1066 part when operated with tCYCLE = 2.50ns
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Version 1.4 July 2002
K4R571669D/K4R881869D
Timing Parameters
Table 13: Timing Parameter Summary
Parameter Description Row Cycle time of RDRAM banks -the interval between ROWA packets with ACT commands to the same bank. RAS-asserted time of RDRAM bank - the interval between ROWA packet with ACT command and next ROWR packet with PRERa command to the same bank. Row Precharge time of RDRAM banks - the interval between ROWR packet with PRERa command and next ROWA packet with ACT command to the same bank. Precharge-to-precharge time of RDRAM device - the interval between successive ROWR packets with PRERa commands to any banks of the same device. RAS-to-RAS time of RDRAM device - the interval between successive ROWA packets with ACT commands to any banks of the same device. RAS-to-CAS Delay - the interval from ROWA packet with ACT command to COLC packet with RD or WR command). Note - the RAS-toCAS delay seen by the RDRAM core (tRCD-C) is equal to tRCD-C = 1 + tRCD because of differences in the row and column paths through the RDRAM interface. CAS Access delay - the interval from RD command to Q read data. The equation for tCAC is given in the TPARM register in Figure 40. CAS Write Delay (interval from WR command to D write data. CAS-to-CAS time of RDRAM bank - the interval between successive COLC commands). Length of ROWA, ROWR, COLC, COLM or COLX packet. Interval from COLC packet with WR command to COLC packet which causes retire, and to COLM packet with bytemask. The interval (offset) from COLC packet with RDA command, or from COLC packet with retire command (after WRA automatic precharge), or from COLC packet with PREC command, or from COLX packet with PREX command to the equivalent ROWR packet with PRER. The equation for tOFFP is given in the TPARM register in Figure 40. Interval from last COLC packet with RD command to ROWR packet with PRER. Interval from last COLC packet with automatic retire command to ROWR packet with PRER. Min Min Min Min -32P -32 -35 -40 -1066 -1066 -1066 -800 28 28 32 28
Direct RDRAMTM
Min -45 -800 28
Max
Units
Figure(s) Figure 16 Figure 17 Figure 16 Figure 17 Figure 16 Figure 17
tRC
-
tCYCLE
tRAS
20
20
22
20
20
64sb
tCYCLE
tRP
8
8
10
8
8
-
tCYCLE
tPP
8
8
8
8
8
-
tCYCLE
Figure 13
tRR
8
8
8
8
8
-
tCYCLE
Figure 14
tRCD
9
9
9
7
9
-
tCYCLE
Figure 16 Figure 17
tCAC tCWD tCC tPACKET tRTR
8 6 4 4 8
9 6 4 4 8
9 6 4 4 8
8 6 4 4 8
8 6 4 4 8
12 6 4 -
tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE
Figure 5 Figure 40 Figure 5 Figure 16 Figure 17 Figure 3 Figure 18
tOFFP
4
4
4
4
4
4
tCYCLE
Figure 15 Figure 40
tRDP tRTP
4 4
4 4
4 4
4 4
4 4
-
tCYCLE tCYCLE
Figure 16 Figure 17
a. Or equivalent PREC or PREX command. See Figure 15. b. This is a constraint imposed by the core, and is therefore in units of s rather than tCYCLE.
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Version 1.4 July 2002
K4R571669D/K4R881869D
Absolute Maximum Ratings
Table 14: Absolute Maximum Ratings
Symbol
VI,ABS VDD,ABS, VDDA,ABS TSTORE TMIN
Direct RDRAMTM
Parameter
Voltage applied to any RSL or CMOS pin with respect to Gnd Voltage on VDD and VDDA with respect to Gnd Storage temperature Minimum operation temperature
Min
- 0.3 - 0.5 - 50 0
Max
VDD+0.3 VDD+1.0 100 Note*
Unit
V V C C
Note*) Component : refer to TJ,JC RIMM: refre to TPLATE, MAX
IDD - Supply Current Profile
Table 15: Supply Current Profile
RDRAM Power State and Steady-State Transaction Ratesa Max (1066MHz, 32P/-32/-35)
6000 4 100
IDD value
IDD,PDN IDD,NAP IDD,STBY IDD,REFRESH IDD,ATTN IDD,ATTN-W
Min
Max (800MHz, -40/-45)
6000 4 80
Unit
A mA mA
Device in PDN, self-refresh enabled and INIT.LSR=0. Device in NAP. Device in STBY. This is the average for a device in STBY with (1) no packets on the Channel, and (2) with packets sent to other devices. Device in STBY and refreshing rows at the tREF,MAX period. Device in ATTN. This is the average for a device in ATTN with (1) no packets on the Channel, and (2) with packets sent to other devices. Device in ATTN. ACT command every 8*tCYCLE, PRE command every 8*tCYCLE, WR command every 4*tCYCLE, and data is 1100..1100 Device in ATTN. ACT command every 8*tCYCLE, PRE command every 8*tCYCLE, RD command every 4*tCYCLE, and data is 1111..1111c
-
-
100 150 790(x18)b 730(x16)
80 120
mA mA
-
620(x18) 575(x16) 560(x18) 530(x16)
mA
IDD,ATTN-R
-
700(x18) 650(x16)
mA
a. CMOS interface consumes power in all power states. b. x18/x16 RDRAM data width. c. This does not include the IOL sink current. The RDRAM dissipates IOL*VOL in each output driver when a logic one is driven.
Table 16: Supply Current at Initialization
Symbol
IDD,PWRUP,D IDD,SETR,D
Parameter
IDD from power -on to SETR IDD from SETR to CLRR
Allowed Range of tCYCLE
1.875ns to 2.5ns 1.875ns to 2.5ns
VDD
VDD,MIN VDD,MIN
Min
-
Max
200a 332
Unit
mA mA
a. The supply current will be 150mA when tCYCLE is in the range 15ns to 1000ns.
Page 16
Version 1.4 July 2002
K4R571669D/K4R881869D
Capacitance and Inductance
Table 17: RSL Pin Parasitics
Symbol LI Parameter and Conditions - RSL pins RSL effective input inductance @ tCYCLE=1.875ns RSL effective input inductance @ tCYCLE=2.5ns Mutual inductance between any DQA or DQB RSL signals. L12 LI CI C12 CI Mutual inductance between any ROW or COL RSL signals. Difference in LI value between any RSL pins of a single device. RSL effective input capacitancea @ tCYCLE=1.875ns RSL effective input capacitancea @ t
CYCLE=2.5ns
Direct RDRAMTM
Min 2.0 2.0 4 4
Max 3.5
Unit nH
Figure Figure 63
4.0 0.2 0.6 1.8 2.3 pF 2.4 0.1 0.06 10 15 pF pF Figure 63 Figure 63 Figure 63 nH Figure 63 nH nH Figure 63
Mutual capacitance between any RSL signals. Difference in CI value between average of {CTM, CTMN, CFM, CFMN} and any RSL pins of a single device. RSL effective input resistance @ tCYCLE=1.875ns
RI
Figure 63
RSL effective input resistance @ tCYCLE=2.5ns
a. This value is a combination of the device IO circuitry and package capacitances
Table 18: CMOS Pin Parasitics
Symbol LI ,CMOS CI ,CMOS CI ,CMOS,SIO Parameter and Conditions - CMOS pins CMOS effective input inductance CMOS effective input capacitance (SCK,CMD)a CMOS effective input capacitance (SIO1, SIO0)a 1.7 Min Max 8.0 2.1 7.0 Unit nH pF pF Figure 63 Figure
a. This value is a combination of the device IO circuitry and package capacitances.
Page 17
Version 1.4 July 2002
K4R571669D/K4R881869D
Center-Bonded WBGA Package (92balls)
Figure 4 shows the form and dimensions of the recommended package for the 92balls center-bonded WBGA device class. D A B C D E F G H J K L MN P R S T U
Direct RDRAMTM
Bottom Bottom Top
1 2 3 4 5 6 7 8 9 10 d e1 Bottom E E1 Figure 4: Center-Bonded WBGA Package Table lists the numerical values corresponding to dimensions shown in Figure 4. Table 19: Center-Bonded WBGA Package Dimensions
Symbol e1 e2 A D E E1 d Parameter Ball pitch (x-axis) Ball pitch (y-axis) Package body length Package body width Package total thickness Ball height Ball diameter Min. 0.80 0.80 9.2 15.0 0.98 0.30 0.40 Max. 0.80 0.80 9.4 15.2 1.08 0.40 0.50 Unit mm mm mm mm mm mm mm
A
e2
Page 18
Version 1.4 July 2002

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